Data integrity is an important feature for any data storage device and data transmission. Use of strong error-correction codes (ECCs) is recommended for various types of data storage devices including NAND flash memory devices. ECCs are also frequently used during the process of data transmission.
Error correcting code (ECC) refers to codes that add redundant data, or parity data, to a message, such that the message can be recovered by a receiver even when a number of errors were introduced, either during the process of transmission, or storage. In general, the ECC can correct the errors up to the capability of the code being used.
Solid-state drives (SSDs) use multi-level NAND flash devices for persistent storage. However, the multi-level NAND flash devices can be inherently unreliable and generally need to use ECCs to allow dramatic increase in data reliability at the expense of extra storage space for ECC parity bits. There is a demand for increasingly efficient ECCs that provide the most data protection for the least parity requirements. Generalized low-density parity check codes (G-LDPC) are excellent candidates for use on binary-output channels like the NAND flash memory devices. However, if a G-LDPC decoder is designed to correct for the worst case correction capability, this decoder may not be fast enough and may have a high hardware complexity in terms of processing cycles and power consumption, especially that a significant amount of the errors to be corrected do not fall under this worst case. Hence, there is a need for low-complexity decoding schemes for G-LDPC codes that allow fast decoding for most NAND reads that have a few errors, without the hardware complexity of a decoder designed to correct for the worst case.